Showing posts with label RGTU EC-505 CMOS AND VLSI DESIGN QUESTION PAPERS. Show all posts
Showing posts with label RGTU EC-505 CMOS AND VLSI DESIGN QUESTION PAPERS. Show all posts
RGPV EC-505 CMOS AND VLSI DESIGN PAPERS I RGTU EC 5TH SEM ALL PAPERS I RGTU EC-505 CMOS AND VLSI DESIGN PAPERS I CMOS AND VLSI DESIGN SAMPLE PAPERS I VLSI DESIGN MODEL PAPERS I RGTU CMOS AND VLSI DESIGN PREVIOUS YEAR PAPERS I RGTU EC 5TH SEM CMOS AND VLSI DESIGN OLD PAPERS I RGPV EC-505EXAM PAPERS I CMOS AND VLSI DESIGN OLD EXAM PAPERS I RGTU EC-505 CMOS AND VLSI DESIGN QUESTION PAPERS I RGTU EC 5TH SEM MODEL PAPERS I CMOS AND VLSI DESIGN MODEL PAPERS I CMOS AND VLSI DESIGN TEST PAPERS I RGPV CMOS AND VLSI DESIGN GUESSING PAPERS I RGTU CMOS AND VLSI DESIGN GUESS PAPERS I RGTU CMOS AND VLSI DESIGN PREVIOUS YEAR PAPERS I RGTU CMOS AND VLSI DESIGN EXAM PAPERS I RGTU CMOS AND VLSI DESIGN OLD QUESTION PAPERS I RGTU CMOS AND VLSI DESIGN IMPORTANT UESTION I

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R.G.P.V. BHOPAL
E.C. 5th Semester EXAMINATION
CMOS & VLSI DESIGN EC-505
  • CMOS & VLSI DESIGN EC-505 PAPER-2
  • CMOS & VLSI DESIGN EC-505 PAPER-3
  • CMOS & VLSI DESIGN EC-505 PAPER-4
  • CMOS & VLSI DESIGN EC-505 PAPER-5
META TAGS:-CMOS AND VLSI DESIGN IMPORTANT PAPERS I RGTU CMOS AND VLSI DESIGN IMPORTANT QUESTIONS I RGTU CMOS VLSI DESIGN GUESSING PAPERS I VLSI DESIGN PREVIOUS YEAR PAPERS I RGTU EC 5TH SEM ALL SUBJECT PAPERS I RGTU EC 5TH SEM PAPERS I RGTU EC 5TH SEM OLD PAPERS I VLSI DESIGN PAST YEAR PAPERS I RGTU EC 5TH SEM EC-505 OLD PAPERS I RGTU EC-505 CMOS AND VLSI DESIGN MODEL TEST PAPERS I CMOS AND VLSI DESIGN IMPORTANT EXAM QUESTIONS I RGTU CMOS AND VLSI DESIGN TEST PAPERS

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RGTU CMOS AND VLSI DESIGN PAPERS I EC-505 VLSI DESIGN PAPERS I CMOS AND VLSI DESIGN OLD PAPERS I RGTU CMOS AND VLSI DESIGN MODEL PAPERS I RGTU EC-505 VLSI DESIGN OLD PAPERS I RGTU CMOS AND VLSI DESIGN EC-505 EXAM PAPERS I RGTU EC-505 CMOS AND VLSI DESIGN UESTION PAPERS I RGTU EC 5TH SEM MODEL PAPERS I RGTU CMOS AND VLSI DESIGN SAMPLE PAPERS I RGTU EC-505 CMOS AND VLSI DESIGN GUESSING PAPERS I RGTU EC-505 CMOS AND VLSI DESIGN GUESS PAPERS I RGTU EC-505 CMOS AND VLSI DESIGN LAST 5 YEAR PAPERS I RGTU EC-505 CMOS AND VLSI DESIGN PREVIOUS YEAR PAPERS I RGTU EC-505 CMOS AND VLSI DESIGN PAST YEAR PAPERS I RGTU EC 5TH SEM CMOS AND VLSI DESIGN EXAM PAPERS I RGPV EC-505 CMOS AND VLSI DESIGN MODEL TEST PAPERS

R.G.P.V. Bhopal (MP)
E.C.(5th Semester) EXAMINATION
CMOS AND VLSI DESIGN [EC-505]
Time: 3Hrs     Max Marks: 100     Min Marks: 40
Note:Attempt any 5 questions.All question Carry equal marks.
Q.1.(a) Give in short the answers of the following:
                (i) What is Moore's law 
               (ii) Define sheet resistance.
               (iii) Define Interstitial Diffusion.
               (iv) What should be the value of the ratio Zp.u /Zp.d for an NMOS invertor driven through one or more pass transistors.
               (v) Why is the packing density of MOS transistors more than that of bipplar transistors ?
               (vi) Write the advantages of ion implantation process over diffusion process. [Marks 4]

Q.2. Define the following phenomena associated with MOS transistors:
                (i) Body effect
               (ii) Mobility variation
              (iii) Impact ionization
              (iv) Channel length modulation

Q.3.(a) Describe the process of fabrication of silicn gate NMOS transistor. Clearly illustrate the sequence of processes with proper diagram. ?
       (b) Draw the cross-section of a CMOS transistor showing the parasitic transistor and resistors resulting in latch-up problem. Briefly explain the cause of latch-up.

Q.4.(a) Draw the circuit diagram and stick diagram of the following:
            (i) Two input CMOS NOR gate
           (ii) Three input NMOS NAND gate
       (b) Draw the structure of a Twin Tub CMOS transistor. Write the relative merits of twin tub process over its other counterparts.

Q.5.(a) What do you mean by dynamic CMOS logic?Differentiate it from Domino CMOS logic?
       (b) Explain parity generator circuit with the help of structured design approach.?

Q.6.(a) Illustrate the implementation of ALU functions with adders.?
        (b) Explain in brief, a 4-bit serial parallel multiplier.?

Q.7.(a) Draw and explain the NMOS inverter circuit with its characteristics.Make use of a depletion mode transistor as the load.?
       (b) Explain resistance estimation and capacitance estimation n brief.?

Q.8. Write short notes on any three of the following:
                (i) Czochralski process (CZ process)
               (ii) Mead Conway design rules
               (iii) Dynamic shift registers
               (iv) Modified Booth's algorithm
               (v) Small signal A.C characteristics of MOS transistors
META TAGS:-RGTU EC-505 CMOS AND VLSI DESIGN MODEL PAPERS I RGPV EC-505 CMOS AND VLSI DESIGN SAMPLE PAPERS I RGTU EC-505 CMOS AND VLSI DESIGN GUESSING PAPERS I RGTU EC-505 CMOS AND VLSI DESIGN GUESS PAPERS I RGPV EC-505 CMOS AND VLSI DESIGN LAST 5 YEAR PAPERS I RGTU CMOS AND VLSI DESIGN LAST YEAR SOLVED PAPERS I RGTU EC-505 CMOS AND VLSI DESIGN PAST YEAR PAPERS I RGPV EC-505 CMOS AND VLSI DESIGN PREVIOUS YEAR PAPERS I RGTU EC-505 CMOS AND VLSI DESIGN MODEL PAPERS I RGTU CMOS AND VLSI DESIGN IMPORTANT QUESTIONS I RGTU EC 5TH SEM ALL PAPERS I

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