Showing posts with label RGTU m.tech 1st sem syllabus. Show all posts
Showing posts with label RGTU m.tech 1st sem syllabus. Show all posts
RGPV M.TECH ADVANCE PRODUCTION SYSTEM 1ST SEM SYLLABUS I RGTU M.TECH 1ST SEM ADVANCE PRODUCTION SYSTEM SYLLABUS I RGTU ADVANCE PRODUCTION SYSTEM SYLLABUS I RGTU M.TECH 1ST SEM ALL SYLLABUS I ADVANCE PRODUCTION SYSTEM RGU SYLLABUS I RGTU M.TECH ADVANCE PRODUCTION SYSTEM ALL SEM SYLLABUS I RGTU M.E. 1ST SEM COMPLETE SYLLABUS I RGTU M.TECH ADVANCE PRODUCTION SYSTEM ALL SEM SYLLABUS I DOWNLOAD RGTU M.TECH 1ST SEM ADVANCE PRODUCTION SYSTEM I RGPV MMCM-101 SYLLABUS I RGTU M.TECH ADVANCE MATHEMATICS SYLLABUS I RGPV M.TECH 1ST SEM COMPUTER AIDED PROCESS PLAINING SYLLABUS I RGTU MECHANICAL SYLLABUS I RGTU M.TECH 1ST SEM MECHANICAL ENGINEERING SYLLABUS I RGTU ADVANCE PRODUCTION SYSTEM NEW SYLLABUS I
META TAGS:- RGTU ADVANCE PRODUCTION SYSTEM LATEST SYLLABUS I RGPV M.TECH 1ST SEM ALL SUBJECT SYLLABUS I RGTU M.TECH 1ST SEM ADVANCE PRODUCTION SYSTEM NEW SCHEME SYLLABUS I RGTU M.E. 1ST SEM SYLLABUS I ADVANCE PRODUCTION SYSTEM 1ST SEM COMPLETE SYLLABUS I RGTU MMCM-101 ADVANCE MATHEMATICS SYLLABUS I RGTU ADVANCE MATHEMATICS 1ST SEM SYLLABUS I ADVANCE MATHEMATICS SYLLABUS FOR M.TECH 1ST SEM I RGTU M.TECH 1ST SEM ALL SUBJECT SYLLABUS I ADVANCE PRODUCTION SYSTEM M.TECH SYLLABUS I RGTU M.TECH 1ST SEM ADVANCE PRODUCTION SYSTEM ALL SEM SYLLABUS I RGTU M.TECH 1ST SEM COMPLETE SYLLABUS I DOWNLOAD RGTU M.TECH 1ST SEM COMPLETE SYLLABUS I RGTU M.E. 1ST SEM ADVANCE PRODUCTION SYSTEM LATEST SYLLABUS I RGTU ADVANCE PRODUCTION SYSTEM SYLLABUS IN PDF
R.G.P.V., BHOPAL
M.E./M.TECH 1ST SEMESTER
M.E./M.TECH 1ST SEMESTER
ADVANCE PRODUCTION SYSTEM
META TAGS:-RGTU MMCM-101 ADVANCE MATHEMATICS SYLLABUS I RGTU ADVANCE MATHEMATICS 1ST SEM SYLLABUS I ADVANCE MATHEMATICS SYLLABUS FOR M.TECH 1ST SEM I RGTU M.TECH 1ST SEM ALL SUBJECT SYLLABUS I ADVANCE PRODUCTION SYSTEM M.TECH SYLLABUS I RGTU M.TECH 1ST SEM ADVANCE PRODUCTION SYSTEM ALL SEM SYLLABUS I RGTU M.TECH 1ST SEM COMPLETE SYLLABUS I DOWNLOAD RGTU M.TECH 1ST SEM COMPLETE SYLLABUS I RGTU M.E. 1ST SEM ADVANCE PRODUCTION SYSTEM LATEST SYLLABUS I RGTU ADVANCE PRODUCTION SYSTEM SYLLABUS IN PDFI RGTU M.TECH 1ST SEM PAPERS I RGTU ADVANCE MATHEMATICS M.TECH PAPERS I RGTU M.TECH 1ST SEM PAPERS I RGTU ADVANCE MATHEMATICS 1ST SEM PAPERS I RGTU M.TECH 1ST SEM ALL SUBJECT SYLLABUS I DOWNLOAD RGTU 1ST SEM M.TECH ADVANCE PRODUCTION SYSTEM SYLLABUS
RGPV VLSI DESIGM M TECH 1ST SEM LAB -II IS DIGITAL DESIGN INTERNAL ASSESMENT =25
PRACTIACL EXAM =100
TOTAL =125
LAB -1 IS EMBEDDED SYSTEM DESIGN - INTERNAL ASSESSMENT =25
PRACTICAL EXAM = 100
TOTAL =125
META TAGS;-RGPV M.TECH 1ST SEM VLSI DESIGN SYLLABUS, RGTU M.TECH 1ST SEM EMBEDDED SYSTEM AND MICROCONTROLLER PROGRAMMING SYLLABUS, RGPV MICROCONTROLLER PROGGRAMING SYLLABUS, M.TECH MICROCONTROLLER SYLLABUS, M.TECH EMBEDDED SYATEM SYLLABUS, RGPV M.TECH EMBEDDED SYSTEM AND MICROCONTROLLER PROGRAAMING SYLLABUS I RGTU VLSI DESIGN EMBEDDED MICRO CONTROLLER PROGRAMMING SYLLABUS I RGTU EMBEDDED MICRO-CONTROLLER SYLLABUS
UNIT-I
Embedded System Overview:Embedded System definition.Processor Technology:General purpose,Single Purpose,Application Specific,super scalar,Pipe lined,Very Long Instruction Word (VLIW) Processor, Microprocessors,Micro controllers and DSP Processors.Embedded Processors in VLSI circuit.
UNIT-II
UNIT-II
Architectural Issues:CISC,RISC,DSP and Harvard/Princeton Architectures. Memory :ROM, EPROM,EEPROM,FLASH, RAM,SRAM, DRAM, SDRAM, NVRAM,EDORAM,DDRRAM, Memory Hierarchy and Cache.
Interfacing:Interfacing using Glue Logic,Interrupt,DMA,I/O Bus structure,I/O devices,Serial Communication Protocols,Parallel Communication Protocols,Wireless Protocols.
UNIT-III
Interfacing:Interfacing using Glue Logic,Interrupt,DMA,I/O Bus structure,I/O devices,Serial Communication Protocols,Parallel Communication Protocols,Wireless Protocols.
UNIT-III
Introduction to 8-bit Micro controllers:8051,68HC11, 80196, Timers/Counters,USART. Detailed study of 8051 microcontroller, with its programming in assembly language and Interrupts,Serial Programming etc.
UNIT-IV
UNIT-IV
Interfacing of Micro controller: SPI, PWM, WDT,Input Capture ,Output Compare Modes, Interfacing LED, Switches, ADC, DAC, LCD , RTC. Idea about the C programming of Microcontroller. I2C, CAN bus architecture.
UNIT-V
UNIT-V
Introduction to 16/32-bit microcontrollers:Introduction to ARM Architecture & Organization, Difference between ARM ,ARM9 & ARM11 TDMI,ARM programming model,ARM Instruction set.
TEXT / REFERENCE BOOKS:
TEXT / REFERENCE BOOKS:
- David E. Simon, An Embedded Software Primer, Pearson Education.
- Dr. RajKamal, Embedded Systems, TMH.
- Vahid & Givargis, Embedded System Design,John Wiley & Sons.
- K. J. Ayala , 8051 Microcontrollers, Penram International, Second Edition
- M. A. Mazidi & J. G. Mazidi, 8051 Microcontroller and Embedded System, Pearson Education Asia
- J. W. Valvano, Embedded Microcomputer Systems - Real Time Interfacing, Thomson Asia Pte. Ltd.
- R. H. Barnett, 8051 family of Microcontrollers, PHI.
- Peter Spasov, Microcontroller Technology: The 68HC11, PHI, Fourth Edition
- Dr. Rajkamal, Micro controllers (Architecture, Programming, Interfacing and System Design), Pearson Education.
META TAGS:- RGTU M.TECH 1 ST SEM SYLLABUS FOR VLSI DESIGN, RGPV DSP SYLLABUS, RGPV M.TECH DSP SYLLABUS, RGPV M.TECH 1ST SEM DIGITAL SIGNAL PROCESSING SYLLABUS, RGPV M.TECH VLSI DESIN DSP SYLLABUS, RGPV 1ST SEM VLSI DESIGN SUBJECT SYLLABUS I RGTU VLSI DESIGN 1ST SEM SYLLABUS I RGPV VLSI DESIN 1ST SEM SYLLABUS I VLISI DESIGN DIGITAL SIGNAL PROCESSING SYLLABUS I M.TECH VLSI DSP SYLLABUS
UNIT I
Introduction to Discrete Time Signals:Sequences; representation of signals on orthogonal basis; Sampling and Reconstruction of signals.UNIT II
Discrete Systems:Attributes;Z-Transform;Analysis of LSI systems;Frequency analysis; nverse systems,Discrete Fourier Transform (DFT),Fast Fourier Transform algorithms,Implementation of discrete time systems.
UNIT III
Design of FIR Digital FiltersWindow method, Park-McClellan's method; Effect of finite register length in FIR filter design.
UNIT IV
Design of IIR Digital Filters:Butterworth, Chebyshev and Elliptic Approximations; Lowpass, Bandpass,Bandstop and High pass filters.
UNIT V
Introduction to VLSI DSP:Transformations for high speed using pipelining, retiming, parallel processing, and folding techniques;Design of programmable DSPs.
TEXT / REFERENCE BOOKS
- A.V. Oppenheim and Schafer, Discrete Time Signal Processing, Prentice Hall, 1989.
- John G. Proakis and D.G. Manolakis, Digital Signal Processing: Principle, Algorithms and Applications, Prentice Hall, 1997.
- L.R. Rabiner and B. Gold, Theory and Application of Digital Signal Processing, Prentice Hall, 1992.
- J.R. Johnson, Introduction to Digital Signal Processing, Prentice Hall, 1992.
- D. J. DeFatta, J. G. Lucas and W. S. Hodgkiss, Digital Signal Processing, J Wiley and Sons, Singapore, 1988.
- K.K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, Wiley.
META TAGS:-RGTU VLSI 1ST SEM SYLLABUS, RGTU M.TECH 1ST SEM SYLLABUS, RGPV M.TECH VLSI DESIGN 1ST SEM SYLLABUS, ADVANCED LOGIC DESIGN SYLLABUS, M.TECH 1ST SEM VLSI DESIGN SUBJECTS, RGPV M.TECH 1ST SEM ADVANCED LOGIC DESIGN SYLLABUS I RGPV ADVANCED LOGIC DESIGN SYLLABUS I RGPV M.TECH VLSI DESIGN 1ST SEM SYLLABUS
UNIT I
Course overview:design concepts,introduction to logic circuit and Verilog.Implementation technology,CMOS logic gates,programmable logic devices.Optimized implementations of logic functions,canonical representations ,Karnaugh maps, factoring,functional decomposition, NAND/NOR networks, bubble pushing.
UNIT II
Course overview:design concepts,introduction to logic circuit and Verilog.Implementation technology,CMOS logic gates,programmable logic devices.Optimized implementations of logic functions,canonical representations ,Karnaugh maps, factoring,functional decomposition, NAND/NOR networks, bubble pushing.
UNIT II
Verilog data types and operators:modules and ports gate level modeling,time simulation/ scheduler.Circuit issues.Verilog behavioral models,number representation and arithmetic circuits,positional notation,signed numbers,arithmetic operations.
UNIT III
UNIT III
Verilog specifications of combinational circuits:combinational logic building blocks, encoders / decoders,arithmetic comparison, etc. The basic latch, gated SR and D latch, master-slave and edge-triggered flip flops, counters, shift registers, Design examples, introduction to finite state machines; introduction to Model Sim.
UNIT IV
UNIT IV
Synchronous sequential circuits:design process,state assignment ,hazards, glitches, asynchronous design,Metastability,Noise margins, Power,fan-out,skew Finite state machine design examplesVerilog representations.
TEXT / REFERENCE BOOKS:
TEXT / REFERENCE BOOKS:
- John F. Wakerly, Digital Design, Pearson Education Asia, 3rd Ed.
- M. M. Mano, Digital Design, Pearson Education, 3rd Ed.
- C. H. Roth, Jr., Fundamentals of Logic Design, Jaico Publishing House.
- Fletcher, An Engineering Approach to Digital Design, PHI.
- J. M. Yarbrough, Digital Logic, Thomson Learning.
- Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design, McGraw-Hill Higher Education, 2003, ISBN 0-07-283878-7.
- Samir Palnitkar, Verilog HDL, Prentice Hall, 2nd Edition, 2003, ISBN 0-13-044911-3
TAGS:- RGTU M TECH SYLLABUS, RGPV CMOS VLSI SYLLABUS, M TECH VLSI DESIGN SYLLABUS,RGPV M.TECH 1ST SEM SYLLABUS, RGPV M.TECH 1ST SEM VLSI DESIGN SYLLABUS, CMOS VLSI DESIGN M.TECH SYLLABUS, RGPV ECE M TECH SYLLABUS, DOWNLOAD M.TECH 1ST SEM SYLLABUS I RGPV M.TECH CMOS VLSI DESIGN SYLLABUS I RGTU CMOS VLSI DESIGN M.TECH SYLLABUS I RGTU M.TECH CMOS DESIGN SYLLABUS I RGPV CMOS DESIGN SYLLABUS
CMOS VLSI DESIGN SYLLABUS
UNIT-I
VLSI design methodologies:VLSI Design flow, Design Hierarchy, Regularity, Modularity and Locality,VLSI design styles,Design quality,Packaging technology.MOS device design equations , Second order effects, the complementary CMOS Inverter DC characteristics.
UNI-II
UNI-II
Circuit Characterization and Performance Estimation:Parasitic effect in Integrated Circuits ,Resistance estimation,capacitance estimation,Inductance.Switching characteristics,CMOS - Gate transistor sizing,Power dissipation,CMOS Logic Structures,Clocking Strategies.
UNITIII
UNITIII
CMOS Process Enhancement & Layout Considerations:Interconnect,circuit elements, Stick diagram, Layout design rules, Latchup, latchup triggering, latchup prevention, Technology related CAD issues.
UNIT IV
UNIT IV
Subsystem Design: Structured design of combinational logic-parity generator,Multiplexer, code converters.Clocked sequential circuits-two phase clocking,charge storage,dynamic register element,dynamic shift register. Subsystem design process,Design of ALU subsystem, Adders, Multipliers.Commonly used storage/ memory elements.
UNIT V
UNIT V
Field Programmable Devices:Definitions of Relevant Terminology,Evolution of Programmable Logic Devices,User-Programmable Switch Technologies,Computer Aided Design (CAD) Flow for FPDs,Programmable Logic,Programmable Logic Structures,Programmable Interconnect, Reprogrammable Gate Array, Commercially Available SPLDs,CPLDs and FPGAs,Gate Array Design,Sea-of-Gates.
TEXT / REFERENCE BOOKS:
TEXT / REFERENCE BOOKS:
- D.A. Pucknell, K. Eshraghian, Basic VLSI Design, PHI, 3rd Ed.
- John P. Uyemura, Introduction to VLSI Circuits and Systems, John Wiley & Sons.
- Niel H.E. Weste, K. Eshraghian,, Principles of CMOS VLSI Design, Person, 2nd Ed.
- Mead and L. Conway, Introduction to VLSI Systems, Addison-Wesley.
- A. Mukherjee, Introduction to nMOS and CMOS VLSI systems design, Prentice Hall.
