M.E./ M.Tech. Embeded System and VLSI Design SVITS(INDR)

UNIT I
Course overview:design concepts,introduction to logic circuit and Verilog.Implementation technology,CMOS logic gates,programmable logic devices.Optimized implementations of logic functions,canonical representations ,Karnaugh maps, factoring,functional decomposition, NAND/NOR networks, bubble pushing.

UNIT II

Verilog data types and operators:modules and ports gate level modeling,time simulation/ scheduler.Circuit issues.Verilog behavioral models,number representation and arithmetic circuits,positional notation,signed numbers,arithmetic operations.
 
UNIT III

Verilog specifications of combinational circuits:combinational logic building blocks, encoders / decoders,arithmetic comparison, etc. The basic latch, gated SR and D latch, master-slave and edge-triggered flip flops, counters, shift registers, Design examples, introduction to finite state machines; introduction to Model Sim.

UNIT IV

Synchronous sequential circuits:design process,state assignment ,hazards, glitches, asynchronous design,Metastability,Noise margins, Power,fan-out,skew Finite state machine design examplesVerilog representations.

TEXT / REFERENCE BOOKS:

• John F. Wakerly, Digital Design, Pearson Education Asia, 3rd Ed.

• M. M. Mano, Digital Design, Pearson Education, 3rd Ed.

• C. H. Roth, Jr., Fundamentals of Logic Design, Jaico Publishing House.

• Fletcher, An Engineering Approach to Digital Design, PHI.

• J. M. Yarbrough, Digital Logic, Thomson Learning.

• Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design, McGraw-Hill Higher Education, 2003, ISBN 0-07-283878-7.

• Samir Palnitkar, Verilog HDL, Prentice Hall, 2nd Edition, 2003, ISBN 0-13-044911-3