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Rajiv Gandhi Technological University,Bhopal(MP)
B.E. Electronics & Communication Engg.     
Semester :-V
Subject :- SOFTWARE LAB
Revised Syllabus and Scheme of Examination
Effective from July 2010
                                                          SOFTWARE LAB(EC-506)

SECTION A:
ELECTRONIC DESIGN AUTOMATION SOFTWARE:Introduction to EDA environment, eg.Microwind /Cadence /Sylvaco /Tanner silicon HiPer/ Xilinx ISE 9i /any similarsoftware/Any Freeware -EDA, its study and simulation/analysis/design of circuits. (The EDA tool package should have equal number of perpetual licenses for all modules and should have GUI)

SECTION B:  
VERILOG: Introduction, Language Element, Expression, Gate Level Modeling, User-Defined Primitives, Data Flow Modeling, Behavioral Modeling, Structural Modeling, Synthesize, Verilog Constructs To G ate, Modeling- Combinational Logic, Modeling-Sequential Logic, Modeling A Memory.

SECTION C:  
VHDL:Introduction, Entity Declaration, Architecture Body, Configuration and Package Declaration, Package Body, Model Analysis, Simulation, Basic Language Elements, Behavioral Modeling, Data Flow Modeling, Structural Modeling.

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