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Rajiv Gandhi Technological University,Bhopal(MP)
B.E. Electronics & Communication Engg.
Semester :-V
Subject :- CMOS VLSI DESIGN
Revised Syllabus and Scheme of Examination
Effective from July 2010
CMOS VLSI DESIGN (EC-505)
Unit -I
Introduction:CMOS Logic: Inverter, NAND Gate, Combinational Logic, NOR Gate, Compound Gates, Pass Transistors and Transmission Gates, Tristates, Multiplexers, Latches and Flip-Flops, CMOS Fabrication and Layout: Inverter Crosssection, Fabrication Process, Layout Design rules, Gate Layout, Stick Diagrams. VLSI Design Flow. MOS Transistor Theory: Ideal I-V Characteristics, C-V Characteristics: MOS Capacitance Models, MOS Gate Capacitance Model, MOS Diffusion Capacitance Model. Non ideal I-V Effects: Velocity Saturation and Mobility Degradation, Channel Length Modulation, Body Effect, Subthreshold Conduction, Junction Leakage, Tunneling,Temp. and Geometry Dependence. DC Transfer characteristics: Complementary CMOS Inverter DC Characteristics, Beta Ratio Effects, Noise Margin, Ratioed Inverter Transfer Function, Pass Transistor DC Characteristics, Tristate Inverter, Switch- Level RC Delay Models.
Unit -II
CMOS Processing Technology:CMOS Technologies: Background, Wafer Formation, Photolithography, Well and Channel Formation, Silicon Dioxide (SiO2), Isolation, Gate Oxide, Gate and Source/Drain Formation, Contacts and Metallization, Passivation, Metrology. Layout Design Rules: Design Rules Background, Scribe Line and Other Structures, MOSIS Scalable CMOS Design Rules, Micron Design Rules. CMOS Process Enhancements: Transistors, Interconnect, Circuit Elements, Beyond Conventional CMOS.
Unit -III
Circuit Characterization and Performance Estimation|:Delay Estimation: RC Delay Models, Linear Delay Model, Logical Effort, Parasitic Delay. Logical Effort and Transistor Sizing: Delay in a Logic Gate, Delay in Multistage Logic Networks, choosing the Best Number of Stages. Power Dissipation: Static Dissipation, Dynamic Dissipation, Low-Power Design. Interconnect: Resistance, Capacitance, Delay, Crosstalk. Design Margin: Supply Voltage, Temperature, Process Variation, Design Corners. Reliability, Scaling.
Unit -IV
Analog Circuits:MOS Small-signal Model, Common Source Amplifier, The CMOS Inverter as an Amplifier, Current Mirrors, Differential Pairs, Simple CMOS Operational Amplifier, Digital to Analog Converters, Analog to Digital Converters, RF Circuits.
Unit -V
Combinational Circuit DesignCircuit Families: Static CMOS, Ratioed Circuits, Cascode Voltage Switch Logic, Dynamic Circuits, Differential Circuits, Sense Amplifier Circuits, BiCMOS Circuits, Low Power Logic Design, Comparison of Circuit Families. Standard Cell Design: Cell Hierarchies, Cell Libraries, Library Entries, Cell Shapes and Floor Planning.
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